MicroTESK @ ISPRAS OPEN 2018

New Features
MicroTESK was presented at the Technology Exhibition of the ISPRAS OPEN Conference held in Moscow on November 22-23, 2018. ISPRAS Open is an annual event organized by Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISPRAS). This year's conference was dedicated to the 70th anniversary of Russian Computer Science. On June 29, 1948, the Council of Ministers of the USSR issued the Decree №2369 on organization of Institute of Precision Mechanics and Computer Engineering (IPM and CE) of the Academy of Sciences of the USSR. On December 4, 1948, Isaak Brook, a corresponding member of the Academy of Sciences of the USSR, and his team received a certificate №10475 for invention of the electronic computing machine. On December 17, 1948, the Council of Ministers of the USSR…
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MicroTESK 2.4.44 Released

New Features
MicroTESK 2.4.44 has been released New features are as follows: support for sections stored in separate files (useful for boot generation); decoder generator improvements: decode attribute and bit selection in image. Sections stored in separate files There are supported sections stored in separate files (an argument :file has been introduced). That facility may be useful for boot generation. Decoder generator A primitive (mode or op) is allowed to specify a decode attribute describing how to construct the primitive's arguments from the temporary variables (this is a hint to the decoder generator). It is permitted to select bits of non-immediate arguments in the primitive's image. MicroTESK 2.4.44 can be downloaded from here.
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MicroTESK @ DVCon Europe 2018

New Features
MicroTESK was presented at the Design and Verification Conference (DVCon Europe) held in Munich, Germany on October 24-25, 2018. We reviewed the tool and demonstrated a new feature that allows automatically generating architecture validation suites. DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.  
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MicroTESK @ ICAM 2018

New Features
The MicroTESK team attended the conference “Computer-Aided Technologies in Applied Mathematics” (ICAM) held in Katun, Altai Region, Russia on June 4-8, 2018. We did two presentations on MicroTESK: Alexander Kamkin. Architecture-Level Microprocessor Verification Based on Formal Specifications; Alexander Protsenko & Andrei Tatarnikov. Automatic Test Template Generation Based on ISA Specifications.
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MicroTESK @ RISC-V Workshop 2018

New Features
The MicroTESK-for-RISC-V test program generator was demonstrated at the RISC-V Workshop held in Barcelona, Spain on May 7-10, 2018. https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings/ Alexander Kamkin (PM) and Andrei Tatarnikov (Team Lead) participated in the poster/demo session of the workshop. Here are links to the slides and video: Poster slides (pages 41 – 42): https://content.riscv.org/wp-content/uploads/2018/05/Barcelona-Workshop-Poster-Session-Slides.pdf Poster announcement (time 20:32 – 22:07): https://www.youtube.com/watch?v=ylTA63vPHYU The next RISC-V workshop will take place in Chennai on July 18-19, 2018 at the Indian Institute of Technology Madras.
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MicroTESK @ MTV 2017

New Features
MicroTESK was presented at the Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 11-12, 2017. Mikhail Chupilko presented our work on maintaining ISA specifications in MicroTESK test program generator (introducing generic operations and revision constructs to nML specification language). The purpose of MTV is to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This is the 18th edition of the MTV Workshop, a testament to its success in providing an ideal environment…
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MicroTESK @ Taiwan Tech and WRTLT 2017

New Features
MicroTESK was presented in Taipei, Taiwan. On November 29, Alexander Kamkin, the MicroTESK PM, gave a lecture on architecture-level microprocessor verification at the National Taiwan University of Science and Technology (Taiwan Tech). He considered evolution of test program generators (TPGs), discussed approaches to TPG development automation, and outlined new trends in the area. On December 1, Andrei Tatarnikov, the MicroTESK Core team lead, made a presentation at the Workshop on RTL and High-Level Testing (WRTLT). His talk was about combining multiple TPG engines in the MicroTESK framework. Taiwan Tech was established in 1974 as the first and the best higher education institution of its kind of technological and vocational education system in Taiwan. WRTLT is to bring researchers and practitioners of VLSI testing from all over the world together to…
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MicroTESK for RISC-V’s First Build

New Features
We are pleased to announce the first build of MicroTESK for RISC-V. The build has the following properties: nML specifications of 201 instructions (including pseudo ones); no MMU specification; sample test templates. Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv
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