Month: December 2017

MicroTESK was presented at the Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 11-12, 2017. Mikhail Chupilko presented our work on maintaining ISA specifications in MicroTESK test program generator (introducing generic operations and revision constructs to nML specification language). The purpose of MTV is to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This is the 18th edition of the MTV Workshop, a testament to its success in providing an ideal environment…

MicroTESK for RISC-V was presented at the RISC-V Developers Forum held in Moscow, Russia on December 7, 2017. The event was organized by SOVEL jointly with Syntacore, a Russian company specializing in RISC-V cores.

MicroTESK was presented in Taipei, Taiwan. On November 29, Alexander Kamkin, the MicroTESK PM, gave a lecture on architecture-level microprocessor verification at the National Taiwan University of Science and Technology (Taiwan Tech). He considered evolution of test program generators (TPGs), discussed approaches to TPG development automation, and outlined new trends in the area. On December 1, Andrei Tatarnikov, the MicroTESK Core team lead, made a presentation at the Workshop on RTL and High-Level Testing (WRTLT). His talk was about combining multiple TPG engines in the MicroTESK framework. Taiwan Tech was established in 1974 as the first and the best higher education institution of its kind of technological and vocational education system in Taiwan. WRTLT is to bring researchers and practitioners of VLSI testing from all over the world together to…