MicroTESK @ DVCon Europe 2019

Conferences
The MicroTESK framework and the MicroTESK-based test suite for RISC-V microprocessors (so called RISC-V AVS) were presented at DVCon Europe (Design and Verification Conference and Exhibition) held in Munich, Germany on October 29-30, 2019. MicroTESK for RISC-V: https://forge.ispras.ru/projects/microtesk-riscv RISC-V AVS: https://github.com/ispras/riscv-avs  
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MicroTESK for RISC-V 0.0.9 Released

New Features
MicroTESK for RISC-V 0.0.9 has been released. What’s New? Specifications: Added system registers and the related modes Specifications: Added sample specifications of some vector instructions (consistent with RISC-V "V" Vector Extension Version 0.7.1) Specifications: Fixed bugs in RV64A instructions Specifications: Fixed bugs in RV32{F,D} instructions (FEQ, FLE, and FLT) Test Templates: Added sample test templates for vector instructions Test Templates: Changed structure of directories Test Templates: Fixed a Torture-like template ('synthetics/rvxxx') Tool Functions: Moved branch data generators to TestBase Tests: Test suite uses QEMU4V 0.3.3 MicroTESK for RISC-V 0.0.9 can be downloaded from here. More News We started uploading ready-to-use test programs to github: https://github.com/ispras/riscv-avs Here is the link to MicroTESK’s bug tracker at github: https://github.com/ispras/microtesk
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MicroTESK @ SYRCoSE 2019

Conferences
Our research-in-progress on binary code deductive verification was presented at the Spring/Summer Young Researchers’ Colloquium on Software Engineering (SYRCoSE) held in Saratov, Russia on May 29-31, 2019. MicroTESK is used to specify a target instruction set architecture (ISA) and to extract the symbolic representation of a given binary file.
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MicroTESK @ DUHDe 2019

New Features
Our research on binary code deductive verification was presented at the Workshop on Design Automation for Understanding Hardware Designs (DUHDe), a part of the Design Automation and Test in Europe Conference (DATE), held in Florence, Italy on March 29, 2019. In this work, MicroTESK is used to specify a target instruction set architecture (ISA) and to extract the symbolic representation of a given binary file. Other tools in use include Frama-C, Jessie, and Why3. To demonstrate the approach, we utilize RISC-V, a free and open ISA.  
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MicroTESK 2.4.45 Released

New Features
MicroTESK 2.4.45 has been released New features are as follows: Block-level register allocation constraints; MMU plugin: structures' fields are listed from upper to lower bits. Block-level register allocation constraints This facility is aimed at overriding default settings written in the configuration file. MicroTESK 2.4.45 can be downloaded from here.
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MicroTESK @ RISC-V Summit & MTV 2018

New Features
MicroTESK framework and machine-readable specifications of the RISC-V ISA were presented at RISC-V Summit held in Santa Clara, CA on December 3-6, 2018 and Workshop on Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 10-11, 2018. We reviewed MicroTESK for RISC-V and discussed a couple of its applications: test program generation and binary code verification. RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Each year, the RISC-V Foundation hosts global events to bring the expansive ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the ISA forward. This was the first-ever RISC-V Summit with 1000+ registrants from 20 countries around the globe, 29 exhibitors, and…
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MicroTESK @ ISPRAS OPEN 2018

New Features
MicroTESK was presented at the Technology Exhibition of the ISPRAS OPEN Conference held in Moscow on November 22-23, 2018. ISPRAS Open is an annual event organized by Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISPRAS). This year's conference was dedicated to the 70th anniversary of Russian Computer Science. On June 29, 1948, the Council of Ministers of the USSR issued the Decree №2369 on organization of Institute of Precision Mechanics and Computer Engineering (IPM and CE) of the Academy of Sciences of the USSR. On December 4, 1948, Isaak Brook, a corresponding member of the Academy of Sciences of the USSR, and his team received a certificate №10475 for invention of the electronic computing machine. On December 17, 1948, the Council of Ministers of the USSR…
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