Month: November 2018

MicroTESK 2.4.44 has been released New features are as follows: support for sections stored in separate files (useful for boot generation); decoder generator improvements: decode attribute and bit selection in image. Sections stored in separate files There are supported sections stored in separate files (an argument :file has been introduced). That facility may be useful for boot generation. Decoder generator A primitive (mode or op) is allowed to specify a decode attribute describing how to construct the primitive's arguments from the temporary variables (this is a hint to the decoder generator). It is permitted to select bits of non-immediate arguments in the primitive's image. MicroTESK 2.4.44 can be downloaded from here.

MicroTESK was presented at the Design and Verification Conference (DVCon Europe) held in Munich, Germany on October 24-25, 2018. We reviewed the tool and demonstrated a new feature that allows automatically generating architecture validation suites. DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.