MicroTESK @ RISC-V Summit & MTV 2018

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MicroTESK framework and machine-readable specifications of the RISC-V ISA were presented at RISC-V Summit held in Santa Clara, CA on December 3-6, 2018 and Workshop on Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 10-11, 2018. We reviewed MicroTESK for RISC-V and discussed a couple of its applications: test program generation and binary code verification.

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Each year, the RISC-V Foundation hosts global events to bring the expansive ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the ISA forward. This was the first-ever RISC-V Summit with 1000+ registrants from 20 countries around the globe, 29 exhibitors, and 53 presentations.


The purpose of MTV is to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SoC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This was the 19th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test, security and verification experiences, and innovative solutions.