MicroTESK @ RISC-V Summit 2020

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MicroTESK framework and our ongoing research on online test program generation were presented at RISC-V Summit held online on December 8-10, 2020. The idea is that a generator (at least some part of it) works inside the design under test and constructs test programs on the fly. Each test is supplied with an equivalent mutant, and the CPU is checked by comparing their results.

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Each year, the RISC-V Foundation hosts RISC-V Summit and other events to bring the expansive ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the ISA forward.