Month: December 2019

As usual, December was rich in events for our team. We attended three conferences, one in Russia and two in USA, where we presented MicroTESK in general (core and engines), MicroTESK for RISC-V (tools for test program generation and deductive binary code verification), and RISC-V Architecture Verification Suite, so-called RISC-V AVS (a set of test programs generated mostly by MicroTESK): Ivannikov ISP RAS Open Conference (ISPRAS Open) held in Moscow, Russia on December 5-6, 2019Microprocessor Test and Verification Workshop (MTV) held in Austin, TX, USA on December 9-10, 2019RISC-V Summit held in San Jose, CA, USA on December 9-12, 2019 We are full of plans and looking forward to implementing them next year. Happy 2020!

MicroTESK 2.5.0 has been released. What's new? Introduced new internal representation, so-called MIR (Middle-level [or MicroTESK] IR)Redesigned the constraint generator (for mark-based situations)Redesigned the symbolic executor (for binary code analysis)Unified the directives (alignment, data definition, and labels) for .text and .data sectionsEnabled a possibility to define data in .textImplemented new directives: .balign, .p2align, and .optionRefactored the code/data allocation logicImplemented a simple instruction-level coverage tracker (experimental)Introduced a new option --coverage-log for tracking test coverageEnabled a possibility to generate test coverage reports in Aspectrace format Used the QEMU4V 0.3.4 simulator for running tests Download: http://forge.ispras.ru/projects/microtesk/files MicroTESK for * Updated The dependent projects have been updated: MicroTESK for RISC-V (0.1.0)MIcroTESK for MIPS (0.1.0)MicroTESK for PowerPC (0.0.4) Related Links MicroTESK for RISC-V: https://forge.ispras.ru/projects/microtesk-riscv/MicroTESK for MIPS: https://forge.ispras.ru/projects/microtesk-mips64/MicroTESK for PowerPC: https://forge.ispras.ru/projects/microtesk-powerpc/QEMU4V: https://forge.ispras.ru/projects/qemu4v/