MicroTESK @ MES 2018

Conferences
MicroTESK was presented at the All-Russia Science & Technology Conference "Problems of Advanced Micro- and Nanoelectronic Systems Development" (MES) held in Zelenograd, Moscow on October 1-5, 2018. MES is a biennial conference in design automation of micro-and nanoelectronics. It is a biggest Russian event in the area that provides a unique opportunity, bringing together hardware designers, CAD developers, and researchers.
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MicroTESK @ ICAM 2018

New Features
The MicroTESK team attended the conference “Computer-Aided Technologies in Applied Mathematics” (ICAM) held in Katun, Altai Region, Russia on June 4-8, 2018. We did two presentations on MicroTESK: Alexander Kamkin. Architecture-Level Microprocessor Verification Based on Formal Specifications; Alexander Protsenko & Andrei Tatarnikov. Automatic Test Template Generation Based on ISA Specifications.
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MicroTESK @ RISC-V Workshop 2018

New Features
The MicroTESK-for-RISC-V test program generator was demonstrated at the RISC-V Workshop held in Barcelona, Spain on May 7-10, 2018. https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings/ Alexander Kamkin (PM) and Andrei Tatarnikov (Team Lead) participated in the poster/demo session of the workshop. Here are links to the slides and video: Poster slides (pages 41 – 42): https://content.riscv.org/wp-content/uploads/2018/05/Barcelona-Workshop-Poster-Session-Slides.pdf Poster announcement (time 20:32 – 22:07): https://www.youtube.com/watch?v=ylTA63vPHYU The next RISC-V workshop will take place in Chennai on July 18-19, 2018 at the Indian Institute of Technology Madras.
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MicroTESK @ DATE 2018

Conferences
MicroTESK (more precisely, an experimental part aimed at online test program generation) was demonstrated at DATE 2018’s University Booth exhibition held in Dresden, Germany on March 20-22, 2018. Alexander Kamkin and Mikhail Chupilko demonstrated the MicroTESK framework and its experimental facilities for automating online test program generation. DATE is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems.
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MicroTESK @ MTV 2017

New Features
MicroTESK was presented at the Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 11-12, 2017. Mikhail Chupilko presented our work on maintaining ISA specifications in MicroTESK test program generator (introducing generic operations and revision constructs to nML specification language). The purpose of MTV is to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This is the 18th edition of the MTV Workshop, a testament to its success in providing an ideal environment…
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MicroTESK @ Taiwan Tech and WRTLT 2017

New Features
MicroTESK was presented in Taipei, Taiwan. On November 29, Alexander Kamkin, the MicroTESK PM, gave a lecture on architecture-level microprocessor verification at the National Taiwan University of Science and Technology (Taiwan Tech). He considered evolution of test program generators (TPGs), discussed approaches to TPG development automation, and outlined new trends in the area. On December 1, Andrei Tatarnikov, the MicroTESK Core team lead, made a presentation at the Workshop on RTL and High-Level Testing (WRTLT). His talk was about combining multiple TPG engines in the MicroTESK framework. Taiwan Tech was established in 1974 as the first and the best higher education institution of its kind of technological and vocational education system in Taiwan. WRTLT is to bring researchers and practitioners of VLSI testing from all over the world together to…
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MicroTESK for RISC-V’s First Build

New Features
We are pleased to announce the first build of MicroTESK for RISC-V. The build has the following properties: nML specifications of 201 instructions (including pseudo ones); no MMU specification; sample test templates. Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv
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MicroTESK @ HVC 2017

Conferences
MicroTESK was presented at the tool demo session of the Haifa Verification Conference (HVC) held in Haifa, Israel on November 13-15, 2017. HVC 2017 is the 13th in the series of annual conferences dedicated to advancing the state-of the art and state-of-the-practice in verification and testing. The conference provides a forum for researchers and practitioners from academia and industry to share their work, exchange ideas, and discuss the future directions of testing and verification for hardware, software, and complex hybrid systems. The common underlying goal of these techniques is to ensure the correct functionality and performance of complex systems. HVC is the only conference that brings together researchers and practitioners from all verification and testing sub-fields, thereby encouraging the migration of methods and ideas among domains.
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