MicroTESK for RISC-V

Home / New Features / MicroTESK for RISC-V

Trying to keep up with the times, we started MicroTESK for RISC-V, an open test program generator for the open instruction set architecture (ISA).

Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv.

The first build is expected on the beginning of December.

RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation (http://riscv.org).